This paper proposes an efficient structure for nanoscale silicon on insulator (SOI) MOSFETs. Two P + pockets are considered in buried oxide, a pocket under source region and another under channel. Also an N type region with low doping density is considered inside the drain region. By applying the mentioned modifications in buried oxide, short channel effects such as DIBL and subthreshold swing are reduced. Lattice temperature is successfully managed and controlled. The leakage current, floating body effect, and gain voltage, have better values in comparison with conventional structure. Inserted low doping region lowers the maximum electric field at drain side and consequently lessens the breakdown probability. The proposed device with mentioned modifications is suitable to be used in high-temperature, and low dimensional applications.
