In this paper the new methods in improving the performance of carbon nanotube filed effect transistors (CNTFETs) are reviewed and analyzed for the first time. Nano-meter dimensions of CNTFETs results in challenges such as leakage current, power consumption control, switching speed, short channel effects (SCEs) including drain induced barrier lowering (DIBL) and sub-threshold swing (SS), etc. To reduce these problems, various methods and techniques have been proposed. The new methods reported in the recent literature are comprehensively investigated and discussed. The advantages and drawbacks of these methods are shown. Finally, a general conclusion and a comparative analysis of these structures are presented. The results could widely be used by researchers in the field of electronic solid state devices particularly for CNTFET circuit design and fabrication.
