June 22, 2024
Abbas Rezaei

Abbas Rezaei

Academic rank: Assistant professor
Address:
Education: Ph.D in Electrical engineering
Phone: 083-38305001
Faculty: Faculty ofٍٍ Electrical Engineering

Research

Title
Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications
Type Article
Keywords
Reversible logic Combinational circuits Carbon nanotube field effect transistor Average power consumption
Researchers maryam shaveisi، Abbas Rezaei

Abstract

It is obvious that the design of low power digital circuits is very important. Hence, reversible logic can be used as the great method for reducing power consumption. In this paper, we attempt to present various CNTFET-based reversible combinational circuits such as multiplexers and decoders by simultaneous use of the reversible Fredkin gate and Gate Diffusion Input (GDI) technique. At first, we illustrate the block diagram of multiplexers and decoders according to the definition of reversible gates. Then, we introduce the design approach of CNTFET-based circuits by using the GDI technique. All structures are simulated using Synopsys HSPICE with standard 32 nm CNTFET technology in various conditions including temperature 27 °C, simulation time from zero to 100 ns, and other parameters are the variable. In this work, we investigate the variation effect of supply voltage, temperature, number of nanotubes, and chiral vector in performance evaluation of the mentioned circuits. In addition, the ECPOT analysis is reported. According to the results, the proposed CNTFET-based reversible multiplexers achieve a significant saving in average power consumption (approximately 99.99% for 2:1 multiplexer, 99.95% for 4:1 multiplexer, 99.96% for 8:1 multiplexer compared with the best previous work) and the average power consumption for 16:1 multiplexer is 25.47 nw. The proposed CNTFET-based reversible decoders have high performance in the average power consumption (approximately 99.99% for 2:4 decoder, 99.99% for 3:8 decoder, and 99.22% for 4:16 decoder compared with the best previous work). Moreover, applying these suggested circuits significantly improves the speed, PDP, and EDP of complex arithmetic structures.