This study presents the importance of reversible logic in designing of high performance and low power consumption digital circuits. In our research, the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops are investigated based on carbon nanotube field-effect transistors. All reversible flip-flops are simulated in two voltages, 0.3 and 0.5 Volt. Our results show that the proposed structures have achieved a significant improvement in terms of the number of reversible gates, quantum cost, number of constant inputs, number of garbage outputs, delay and average power consumption. Hence, all these criteria in the second proposed D flip-flop are improved 83.3%, 77.27%, 66.6%, 80%, 83.3%, and 99.9%, respectively, and for T flip-flop are reduced 33.3%, 73.68%, 66.6%, 80%, 33.3%, and 82%, respectively. Also, the maximum reduction for the mentioned parameters in the SR flip-flop are 66.6%, 68.16%, 33.3%, 75%, 65.65%, and 60.46%, respectively. Finally, the JK flip-flop parameters are respectively improved by 20%, 52%, 0%, 25%, 20%, and 81%. The Hspice_H-2013.03-SP2 software was used to simulate these circuits and the 32nm CNTFET technology (the standard Stanford spice model).
